Design Of With Skip Cycle Voltage Mode Monolithic Buck DC/DC Controller

The switch mode regulated power supply is one kind of voltageconverter device, it can rise or down the system voltage to suitable one forloading chip on system use. The same time, it also has below obviousadvantages: the stable output voltage, high integration density, seldomperipheral device are need on system PCB, high conversion efficiency, andso on. it is used in many kinds of electronic system widely. In recentyears, as long as so many kinds of portable electronic system supplied bybattery increased dramatically, more stricter requirement towards powermanagement system arise. For example: more high efficiency, more lowpower waste, monitors all output circuit states with more rapid response. Soswitch regulated power becoming a indispensable device for building asystem, also he have replaced low efficiency linear regulator in so manyplaces step by step.This paper just show the design of one kind of voltage-mode buckDC/DC based on the basic theory of switch regulated power supply with the direction of his feature. This design has use some kinds of way toincrease the preference in rise efficiency, low power waste, monitor alloutput current with more rapid response.1. How to raising the efficiency: Each switch cycle of the DC/DC willgive the Inductance and capacitance little energy follow the small dutycycle with the light loading. That is to say the power FET is shut at onceafter open. So, many energy are wasted on the charging the gate of thepower FET. This is one main reason of why efficiency is hard to increase inlight loading. To avoid this kind of shortage, i have designed one kind ofmode named “Skip cycle mode”. The detail is: Each cycle has the least ONtime limitation, but only the output voltage reach to a low threshold voltagethe Power FET can be open again, this kind of design can avoid power FEThas been open at each cycle, then there are no peak current at each cyclewhen open the power FET, in this way the useless power consumption areavoided.2. This design is Synchronization BUCK DC/DC with external powerdevice. When the NMOS power FET entering follow current time, thisdrain voltage of this NMOS’s is negative. This brings troubles to make judge for whether follow current is over current for signal supplied chip.This paper will introduce one kind of negative voltage sampling andmonitor threshold voltage, then use these two data for special calculationafter that give out two positive voltages to make judge for whether overcurrent.3. This design is synchronization voltage mode BUCK DC/DC, outputLC filter has double pole, through careful designed compensation pole andzero with TYPE3compensation to gain the maximum band width with astable loop the same time rise the ability of transient response.