A 65 - Nm Design Of Low Dropout Linear Regulators

The style and functionality of portable electronic products change with each passing day. The power management chip becomes very important with so many and complex functional applications. Low dropout linear regulator (LDO), also known as LDO, is one of the many power management chip designs. Because of its characteristic of low noise, low-cost, small ripple, the high precision, and simple design, low dropout linear regulator has been widely used in the communication equipments, automotive electronic products, and industrial and medical equipment industries.A customized, low-dropout linear regulator with ESD protection circuits based on SMIC65nm process technology is presented in this paper. This LDO can produce a stable output voltage of1.2V with the maximum load current of100mA when the input voltage from2.5V to3.6V. ESD test results are HBM greater than8KV and MM greater than525V. Latch up test result is greater than300mA.The important parameters of the low dropout linear regulator are reviewed and the basic principle of the LDO is described. The specification of the design is defined before the implementation. Then the analysis of the working principle of sub-circuits, such as band gap reference voltage source and error amplifier and so on is given. The SPECTRE tool is used to design the schematic, simulate circuits and verify each sub-block. The details of the layout-related effects after the process improvement, such as DFM, WPE and so on are considered. In addition, the detailed ESD layout rules are also presented. Finally, the taped-out chip is tested and the LDO performance has been verified, the results show that this design not only meet the design specification but also satisfied for customer requirements.