Research And Design Of LDO And Power Manager For RF SOC

Recently, communication chip of Radio Frequency (RF) is widely used in many elec-tronic products, which develops in the direction of System on Chip (SOC) continuously.Meanwhile, the high requirements of the power management in the communication chip ofRF SOC are increasing. As a common Direct-Current (DC) power supply, the low drop-out(LDO) liner regulator has the characteristics of output stability, low noise, easy integration,and so on. Based on these characteristics, the integrated LDOs and strategy of power man-ager have been researched and designed in this paper, which was in RF transceiver chip.Firstly, a brief introduction about the development and classification of powermanagement is given in the first chapter, especially the application, status and developmenttrends of LDO. In the second chapter, the basic theory and performance indexes of LDOare analyzed and discussed in detail. Considering these and the practical application of theRF transceiver chip, the strategy of low power and low noise power manager is presentedin the third chapter, which includes division of power supply regions, digital control, andstandby power switch systems. And, the specific indexes of LDOs are set in accordancewith the different requirements of loads.Then, according to the specific indexes, the main circuits in LDO were researched anddesigned, including pass transistor, error amplifier, band-gap reference (BGR) etc. In orderto reduce the noise of the output voltage of BGR, a special RC filter was designed, whichhad a low bandwidth and also could start-up quickly. The whole circuits were designed andsimulated. The front-end results were good, so the layout of the circuits were designed andsimulated too. The post layout simulations show that: under the operating temperature(-40℃~85℃) and supply voltage (2~3.6V), the temperature coefficient of BGR is less than40×10-6V/℃and the output voltage range of LDOs is1.764~1.848V. The start time ofLDO_PA is1.98μs, the output noise of LDO2and LDO3are49.46μVrmsand99.3μVrmsrespectively, and the quiescent current of LDO3is only21.5μA. Also, the PSRR of analogLDO can reach60dB. These results fulfill the requirements of different LDOs entirely.Finally, the proposed LDOs have been fabricated in the SMIC0.18μm RF CMOStechnology. Test results show that under the supply voltage，the average output voltage ofBGR is1.266V and the average output voltage of LDO is1.79~1.882V. The start time ofLDO_PA is1.74μs, the switching time between LDO3and standby power is less than148μs; the noise characteristic of LDO1is good, the quiescent current consumption of LDO1~LDO3is about0.03mA and the LDO_PA is0.111mA. In short, the powermanagement system and proposed LDOs can be used to supply the power energy to the RFSOC transceivers, since they are featured of stable output voltage, less static powerconsumption, and good noise suppression ability.