Design Of Floating-point Coprocessor IP Core Based On FPGA

Floating-point co-processor is an integral part of the architecture of modern microprocessor, usually cooperates with the main processor to complish certain high-speed and high precision numerical calculations. ASIC designs of floating-point co-processor usually have high performance, but cannot avoid the limits of long design cycle, high implementation cost, inflexibility, therefore are not suitable for cost and flexibility sensitive applications. FPGA is a semi-custom intergrated circuit, which has the characteristics of short development cycle, low cost, low risk, high flexibility and online programming, which ASIC does not have, while has more gates than other programmable logic devices in the scale. IP core is an integrated cicuit core, which has intellectual property. It is a macro module with specific functions verified repeatedly, which has nothing to do with the chip manufacturing process, feasilbe to various semiconductor processes. The rapid development of integrated circuit technology makes FPGA technology become more mature, and FPGA-based IP core more widely used.This paper studied and developed an FPGA-based floating-point coprocessor IP core, implemented 32-bit single-precision floating-point operations such as floating-point addition, subtraction, multiplication, division, square root, etc, supporting four rounding mode: rounding to the nearest even, rounding to zero, rounding to positive infinity and rounding to negative infinity. Three-stage pipeline design techniques were applied to increase the performance of the addition operation from 58.3MHz in the single-cycle design to 131.5MHz in the pipeline design, 79.8% higher than other designs, and the multiplication operation from 69.3MHz to 123.8MHz, 54.7% higher than other designs. Multi-cycle algorithms were used to impelment the division and square root operations, 100.0MHz and 96.1MHz respectively. All floating-point operations were simulated by 2 million test vectors generated by a third party floating-point test suite, were validated to be logic correct. The design prototyping validation performed in Virtex-5 FPGA development board, indicated the functions of the IP core consistent with the simulation results and the performance consistent with the timing analysis. The design gave full play to the advantages of FPGA, characterized by short development cycle, portability, etc, feasible for applications in real-time data processing filed, which demands high flexibility.