The Design Of Ethernet Controller IP Core Based On Avalon Bus

This topic mainly discussed the design of IEEE802.3MAC layer and PHY layer onFPGA. The MAC layer supports full-duplex mode. The PHY layer supports10BASE-T andAuto-Negotiation. In chapter2, we introduce the protocol of802.3fast Ethernet, includingMAC layer and PHY layer. In chapter4, we give the requirement analysis, moduleidentification, module design, module realization and simulation result of the IP core. Inchapter4, we give the scheme and result of integration test.This topic gives the detail discrimination and realization method of many modules, suchas transmission module, reception module, check module, txrx buffer module, register module,bus connector module, and connector from MAC to PHY in the MAC part. Such as theconnector from PHY to MAC, Manchester encode/decode module, Auto-Negociation module,transmission control, reception control in the PHY part.Verilog HDL is used to realize all the modules. Source Insight3.0is used to write code.Quartus9.1is used to compile, simulate and download to dev board. SOPC builder is used togenerate a Nios II CPU and other IP core that needed by the dev board. Cyclone III FPGA isused for verification and validation of the IP core.The top-down method is used for design. The software engineering method is used forthe developing flow control, such as unit test, integration test, iterative modify.Clock domain crossing transfer problem is discussed to give the method of transmissionbetween MAC and PHY.Optimization is implementated with the advantage of FPGA. Pipe line structure is usedin the transmission and reception. So receiving, check, moving, reading module can work inparallel. In the design of bus connector module, the IP core is compatible with DM9000.