Design Of Hardware Acceleration IP Core For RC4 Encryption Algorithm

With the extensive use of FPGAs,the security function of communication is paid more and more attention.Using the corresponding encryption algorithm such as RC4 algorithm to achieve its security in the communication is the only choice.But no matter what kind of encryption algorithm,encryption or decryption will be a lot of computation,which will greatly increase the burden of CPU.Especially for some specific applications,through the preparation of the corresponding hardware-accelerated IP core to solve the encryption algorithm for the corresponding problems brought about by the positive significance.As the direct use of HDL language RC4 encryption algorithm to achieve hardware-accelerated IP core is very difficult,this paper uses C language algorithm,the algorithm is verified by the relevant tools into HDL module to greatly simplify the IP core design.This paper discusses the implementation of RC4 encryption algorithm C and related software testing methods.On this basis,we analyze the HDL file generation of RC4 algorithm,realize the interconnection with Avalon bus and RC4 encryption algorithm to accelerate IP core SOPC component generation.The design of the SOPC system is described.The content includes the reasonable configuration of the Nios II processor,the SDRAM controller,the clock PLL,the communication port and so on.The software and the hardware performance test program are written to realize the final system integration,And completed a comprehensive test system.Experimental results show that,even in the case of compiler optimization,RC4 encryption algorithm hardware-accelerated IP core and pure software implementation compared to nearly twice the efficiency of the upgrade.If the algorithm XOR also hardware implementation and with the DMA,the acceleration effect is even better.The method discussed in this paper greatly simplifies the design of IP core,and explores a feasible way to speed up the design of IP core.