A Low-Cost Delay Testing Methodology Based On Scan Chain Disabling Technique

Testing can effectively guarantee the reliability of circuits. It is an indispensable part of the integrated circuits(IC) industry chain which involves design, manufacturing, testing, and encapsulation. With the development in semiconductor industry, the test cost gets higher and higher. Thus, the low-cost technology is of significant importance to the IC industry. It has been a heated research subject around the globe.This thesis is conducted to explore the low-cost technology for delay test. Some methods based on scan chain disabling technique have been proposed to reduce test power. Among them, some methods are put forward for the stuck-at model. Others need extra control signals, which increase the test data volume, thus increasing the test cost.To overcome these problems, this thesis taking previous theoretical findings as the foundation, analyzed the basic principles in IC test and then proposes a turn-capture delay test based on scan chain disabling technique. In this method, all sequence elements are divided into N scan sub-chains(N representing any positive integer), so as to decrease the length of the longest sub-chain to one N-th of that with a single scan chain. Not all scan sub-chains need to be active in testing. Therefore, the division of sub-chain makes some sequence elements inactive in test model. In test mode, there are two operating modes. One is that only one sub-chain works, while the other is that all sub-chains work. However, all scan chains work at the same time in traditional method. This method can effectively depress the test application time with a low-cost on hardware.Finally, experiment is performed to analyze our proposed method. It demonstrated that the method can drastically reduce test application time while maintaining low test power and high fault coverage. It also manifests that given circuits of different scales and sub-chains of the same number, the larger the circuit scale is, the higher the coverage and the lower the application time is, and that given the same circuit, the more the sub-chains are, the lower the test application time is and less testing data are.