Design For Test Based On Scan Chain Of IP Core And Research On Test Coverage

With the development of integrated circuit design and manufacturing technology,the integration and scale of chips have improved significantly.Meanwhile,the probability of physical defects per unit area will also increases because of the increasing of transistor density.To detect the faults in circuits,a new testing technique named design for test is adopted,which is based on scan chain.By adding auxiliary circuit,the common flip-flops in the circuit are replaced by the scannable ones,so that the sequential logic circuits which are difficult to test will be changed into combinational logic circuit which can be tested easily.However,some problems remain in the testing technique because of large chip-scale and complex circuit system,such as low test coverage,long test time,and using too many test pins.How to use limited testing resources to improve the test coverage and reduce the cost of testing has become one of the problems that need to be solved urgently.The goal of this thesis is to improve the test coverage of ATPG,which is based on classical test methods for performance improvement and optimization.To realize this goal,the thesis expounds the principle and structure of design for test technique firstly,and then analyzes the characteristics of the IP core.Finally,the architecture of this testing system is designed and implemented.Based on this,the traditional test methods are optimized through simulation,improving the test coverage and reducing the test cost of circuit.According to the characteristics of the IP core,the corresponding testing methods are formulated: The scan chain is compressed to reduce the length of the internal scan chain because of limited number of test pins;For multi-clock domain in the circuit,PLL is used to generate the high-frequency clock that becomes an output to each clock domain through the frequency divider,which reduces the performance requirement of ATE;To meet the test requirements of different fault models,an on-chip clock control circuit is designed to switch the required test clock.The insertion of scan chain,generation and verification of test vectors are completed,and the final test coverage report is analyzed.The optimization of test coverage is studied by modifying the compression ratio,adding wrapper chain,inserting test points,and controlling the number of test vectors.The methods are analyzed theoretically and simulated,and the test cost is considered while ensuring the test coverage to obtain the best solution:(1)For the limited test pins of the circuit,the compression logic is added.An optimization method of compression ratio is proposed to study its influence on test coverage;(2)For the uncontrollable and unobservable nodes at the port of circuit,a wrapper chain structure was added to make it into a controllable and observable node,thus test coverage of the circuit at the port is improved;(3)For the uncontrollable and unobservable nodes existing within the circuit,increasing the testability by test points insertion.And the influence of the number of test points on the test coverage is studied;(4)For a large number of test vectors in testing,a new strategy is applied to decrease the number of test vectors.Test time is decreased on the premise of ensuring the test coverage.Based on the simulation results of these solutions,the methods proposed in this thesis have a significant effect on optimizing test coverage:(1)Changing compression ratio has a very small impact on test coverage by about 0.06% while reducing the test time by 16.44%;(2)Adding wrapper chain can increase testability at the port of circuit with less area overhead,which increases the test coverage by 1.84% and reduces the test vectors by 8.46%;(3)Test points insertion increases the testability of the nodes within circuit,which can increase the test coverage by 1.29% and reduce the test vectors by 39.52%;(4)When there are a lot of test vectors,the loss of 0.68% of test coverage can reduce 14.76% of test vectors under the premise of ensuring that the test coverage.In conclusion,these four methods above have achieved the testing goal,and have important reference value to the high-quality testing of chips.