Design And Implementation Of A Dynamic Fault Tolerant Router For Network-on-chip

With the development of integrated circuits technology, multi-corearchitecture has become the main trend of processor design. Currently, thescalability is poor in on-chip bus communication mechanism and has beenthe bottleneck of the performance. Network on Chip was introduced toreplace the traditional bus for its high bandwidth and low latency, and isthe most promising method. At the same time, as the chip size reaching thenanometer level, it brings many challenges such as soft error to NoCdesign. If we do not use fault tolerant design, the reliability of the systemwill decline. So the design of reliable NoC becomes necessary.In this paper, we learn the mechanism of soft error and NoC. And wefind the virtual channel which occupies most of the area is the mainprotection part. Then we define the reliable router of NoC to be researchdirection, and the dynamic reliable virtual channel architecture is firstlyproposed in this paper. It can detect the utilization of the virtual channel toadjust configuration to support for different requirements in flexibility. Theproposed design can use transverse structure when the load of NoC is lowto improve the throughput, and when the load is high it can be switched tovertical structure to reduce the congestion. At last, we finish the design andimplementation of the reliable router by Verilog HDL and redesign thepipeline structure. At the same time, we finish the simulation on Nirgamplatform. Compared with traditional transverse or vertical structure, theproposed design can get good performance at low and high load. Thesynthesis results show the extra area cost can be in acceptable range.