High-performance On-chip Interconnect Structure Design

High-speed data transmission puts forward higher requirements on interconnectdesign. The tradition RC interconnect cannot meet high-speed and low-powerrequirements of GHz chip. Meanwhile, signal integrity problems such as reflection,crosstalk, inter-symbol interference (ISI) and attenuation restrict improvement of chipperformance. The application of transmission line technique provides new feasiblesolution to the bottleneck and challenge in chip design. Therefore, the study ofhigh-speed on-chip interconnect design is quite essential.According to the structure of differential transmission line (DTL) in nanometerCMOS process, this paper extracts interconnect parasitic and coupling parameterswhich considers skin effect. Then, a novel parallel RLC interconnect model consideringcoupling capacitive and inductive effects is proposed. By analyzing this model, theexpression of DTL loss is obtained which can be used in nanometer SOCs, and therelationship between interconnect size and attenuation is also given. Compared withHFSS simulation in65nm process and measured results in180nm process, the proposedloss model enables4.24%,6.48%average error respectively. For reducing couplingnoise, we describe the interconnect design of crosstalk avoidance. In terms ofinterconnect transceiver, pre-emphasis transmitter and continuous time linearequalization is adpoted, and in order to further improve received signal quality, thispaper completes adaptive digital transceiver design through using least-mean-squarealgorithm. Simulation result shows that the transceiver overcomes ISI phenomenon andcompensates up to-13dB interconnect attenuation in10Ghz, and10Gbps on-chip signaltransmission can be achieved by the design.