The Parallel Design And Optimization Of H.264Intra Prediction Based On FPGA

H.264has become the most mainstream video compression standard which showsgood network affinity in bit rate. However, H.264is able to get such superiorperformance due to the contribution of significant increase of computing complexity,which is about three times as H.263. As recent growth of image quality requirements,DSP’s processing power becomes out at elbows in the face of High Definition or evenUltra High Definition video sources. The most particular characteristic of FPGA isparallel processing ability, besides, FPGA has quite strong ability on processingcomplex logic, and it is rich in I/O and logic resources. During the continuousdevelopment of large scale integrated circuit, the size of FPGA logic resource growseven larger while the cost falls, the video image processing based on FPGA graduallybecomes the focus of research.This thesis proposed an intra predict architecture of mode parallel compute (MPC)based on the systematic analysis of the key technology of H.264. This architecture canavoid repeated computation of the intermediate values by analyzing all the9intraprediction modes at the same time, both simplified the intra prediction, and reduce theconsumption of resources. The synthesis and simulation results on the xc5vlx330thardware platform show that, this architecture uses up20177slice registers,35475LUTs, and10223Slices. This architecture is able to reach the highest workingfrequency of219MHz, and every macroblock takes657cycles to be predicted.According to the100MHz of the working frequency of the whole encoder, thisarchitecture achieves1080p@18fps.Based on the above scenario, this thesis further proposes an intra predictarchitecture of macroblock pipelined process (MPP), while finally achieves amacroblock pipelined architecture of degree2. The architecture processes twomacroblocks without data dependencies at one time, its resource consumption increasenearly15%, while the prediction time reduced about50%compared to the MPCarchitecture. The synthesize and simulation results on the xc5vlx330t hardware platformshows that the highest working frequency of the architecture is186MHz, every twomacroblocks need710cycles to be predicted, which means each macroblock only need355cycles. According to the100MHz of the working frequency of the whole encoder,this architecture can achieve1080p@30fps, which supports real-time coding.