As a new generation of video compression standard, H.264/AVC has a higher compression ratio. However, the complexity of the encoder rises sharply.lt is very important to implement the H.264video codec on FPGA which can complete much complex and real-time codec.This thesis studies the FPGA implementation and optimization of the transform quantification and entropy coding in H.264. First of all, three FPGA design structure for4x4transform is gived and finally the four-stage pipeline structure is selected. Cascading the four transform and quantization submodule in reconstruction loop as a module implementes a joint performance simulation.Then,the CAVLC coding is analyzed and the zero jump and the VLC table optimization method is provided. Finally,the parallel coding idea between the RunBefore-coding and the Level-coding stage is presented for non-zero blocks data.In ISE12.3platforms, transform quantization and Entropy coding is implemented using Verilog HDL language and and a large number of data is being tested for them.The experimental results show that the four-stage pipeline has the maximum frequency as high as506.124MHz, the transform and quantization submodule in reconstruction loop as high as238.308MHz and CAVLC coding module as high as238.308MHz,which can meet the high-definition video encoding requirements. |