The Research For Full-Custom Layout Design Of Vlsi FPGA Chip Under DSM Condition

As a FPGA chip, HWDXXX is one of the high density series productions of CSMT.This paper selects this FPGA product as an instance to analyze the design method ofVLSI which was manufactured in DSM condition and designed by full-custom method.The layout design is an extremely important position in the integrated circuitdesign process. The layout is a process to change the circuit design into a physical chip.The development of integrated circuit process has led to the rapid progress of modernintegrated circuit technology, but also to put forward higher requirements to the designand manufacture of integrated circuits. And the designers of integrated circuit are alsofacing a higher challenge. The choice of materials, craft processing technology and thetype of devices that have been chosen in the design will also do impacts to theperformance of the chip. When the feature sizes have been turned into DSM level, theimpacts of the factors which have been mentioned above will be more and moreobvious. And even they may lead to the chip performance instability or device failureconsequences. In order to improve the chip performance and enhance the reliability ofthe product, it is necessary to learn and research the layout design under DSM process.In the consideration of the characteristics with large scale and high repeatability ofmodules, the design method of FPGA chips is different with other chips. In order tocontrol the area effectively and to get lower power consumption and faster speed of thechips, ordinarily we choose full-custom design method which is in less efficient butmore flexible. At the same time, we can achieve the goals through manual intervention.This is very different with the layout design method (half-custom design method) ofgeneral chips.When integrated circuit design has turned into the DSM phase, the effects whichcan be ignored in design before are becoming more and more important to theperformance of our chips. They may even become to be the critical factors that candecide if the design is successful. Through introducing the layout design method of akind of very large scale FPGA chip of high density, this paper does some research andanalyze of the critical factors which can make influences to the chip. The discussion content includes: device match, parasitics parameters, antenna effect, latch-up effect,ESD protection structure of the chip and crosstalk noise. Combine with the process oflayout, floorplan, verify and LPE, with the experience of layout design, discusses howto decrease or avoid the factors in integrated layout design. The goal of this paper is toget a FPGA chip with correct function and excellent parameters. In the chip that hasbeen produced, the ESD protection capability is a little weaker than it was expected.After careful analysis and research, this paper has given effective advice and the resultof the advice will be verified in the next producing. The layout design method that givenby this paper can be widely used in the DSM very large scale FPGA chip layout design.