The Design Of Multi-channel Sequential Control Signal Generator

With the rapid development of modern science and technology, data acquisitionand processing technology is applied more and more widely. But because of therequirements of scientific research and and the actual project, single channel dataacquisition has been unable to meet the design requirements, especially now many highresolution methods are based on the data of the multiple channels, and data phasecoherence requirement of the multiple channels is very high, so multi-channel analogsignal must ba sampled synchronously in the project implementation. The design, whichis involved in this article, uses an ADC in each channel, the subsequent processorcontrols the operation of data transfer of multiple channels, the purpose of this design isto complete the multi-channel synchronous trigger control.In this article virtex-5FPGA of the Xilinx corporation is the core of the design, anda multi-channel timing control signal generator is designed, which controls thesynchronous trigger control of the multi-channel sampling. The hardware designscheme of signal generator is gived. Combining with the performance requirements ofthe device, the key chips are selected. In this paper the specific schematic design ofsignal generator is gived, it includes the input clock level conversion module, RS-232serial communication level conversion module, Virtex-5FPGA chip with its peripheralcircuit module, the single channel differential signal to the multi-channel circuit moduleand a power supply circuit module. After the completion of the schematic design, all ofsymbol package were produced based on the chip data sheets. If the path of symbolpackage was setted, netlist was imported into the circuit board, and layout and wiringwork was completed.This paper also gived the software design of the virtex-5FPGA, the design toolwas the Xilinx’s ISE13.3software. First, the principle of RS-232serial communicationwas analyzed, the specific design of the UART was gived, each of the modules of thedesign was described in detail, and then a cache RAM module of the control word wascompleted, and finally the timing control signal generating modules wans finished, theModelSim was used to complete the function and time sequence simulation of eachmodule. The software program was downloaded to FPGA chip, and it was debuggedand analyzed. The results were compared with the performance of the design, whichshowed that the accuracy of the system design. The done work was summarized, andput forward some further improvements advices.