Design And Simulation Of Multi-core DSP Parallel Route Planning Based On Route Segments

In order to respond to the rapidly changing battlefield environment, and to adapt to the change of mission, it needs route replanning for the aerial vehicle according to changes in the battlefield environment or mission changes. That is, online planning. Planning speed are very demanding for online planning. In order to solve the problem of planning speed, it need to improve planning method on one hand, and improve hardware performance of planning system on the other.In terms of planning method, the route planning method based on route segments is a method to improve the planning speed. This method uses phased planning. The first phase is construction of route segments, and the second is route reorganization. The first phase can be offline conducted in advance, and then in the second phase conducted online, it can quickly generate a track that meet specific conditions, combined with changes in the battlefield environment and mission, using the route segments constructed in the first phase. It can greatly improve the planning speed by just executing the second phase online. In terms of hardware, the DSP has strong data processing capabilities, and it is suitable for route planning. In recent years, with the development of chip technology, multi-core chips are emerging, and DSP also began to enter the multi-core era. Multi-core DSP with the advantages of high-performance, low-power-consumption and small-size, meets the requirements of the online route planning.Firstly, this study analyzes the purpose and significance of the parallel route segments planning based on the multi-core DSP, with the research status at home and abroad combined. Then the study introduces the major steps of route segments planning as well as the improvements made for DSP. Next, it designs route reorganization method based on the A*search algorithm with some simple optimization implemented. Finally, parallel route planning method based on multi-core DSP is designed, according to the features of multi-core computing. Experiments are conducted on the simulator of the multi-core DSP, TMS320C6678of TI, using the software Code Composer Studio v5.0.2and the experimental results are analyzed as well.