Research On On-line Detecting Methods Of Faults Reside In Digital Circuits

Advances in Very Deep SubMicron(VDSM) have led to impressive performance gainsof Very Large Scale Integration(VLSI) circuits, the development of VLSI also make thembecome more and more practicable in modern society. However the advances insemiconductor have also conctributed to increased rates of occurrence of faults. Design-For-Test (DFT) techniques have been proposed in the design phase of VLSI to improve thereliability. The dissertation describes three on-line test techniques which are on-line Built-In Self-Test (BIST), Totally Self-Checking (TSC) and on-line test based on scan design.On-line BIST techniques are proposed for combinational circuits in the dissertation.Comparator-based Response Analyzer (CBRA) is proposed to reduce the concurrent testlatency and an universal applicable method is also presented to lower the hardwareoverhead. In order to make all of the combinational circuits detectable by the proposedmethod, a novel test control unit is presented in this paper. Experimental results show theexcellent detecting efficiency of faults reside in VLSI.In some certain applications which reliability is most significant parameter, bothfaults in Circuit-Under-Test (CUT) and test circuits need be detected as soon as possible,TSC on-line test techniques are proposed to resolve this problem in this dissertion. TSCfunctional circuit and TSC checker are studied separately in this paper and theiridiographic realized methods are also presented. Results of the verification platformshow that faults exist in TSC functional circuits and TSC checker can be detectedeffectively.On-line test method based on Scan design is proposed specially for sequential circuits.The novel scan unit can resolve the problem exist in the previous methods that they canonly perform nonconcurrent test, however the novel scan unit can also bring great gains ofharedware overhead. Similarly to the on-line BIST method, an input/output optimizingmethod is proposed to increase the feasibility. Experimental results indicate that comparedto the previous methods, the novel scan have less hardware overhead and can perform theconcurrent test along with detecting the faults existed in CUT.