Hardware Circuit Design Of A Built-in Test System For Communication Equipment

With the development and progress of information technology and semiconductor technology,the proportion of integrated circuit in equipment is higher and higher.In order to ensure the reliability and safety of the equipment,testability design must be considered in the circuit design.Communication system is the core module that directly determines whether the equipment can work normally,so it is very necessary to design the built-in test system for communication equipment.The purpose of built-in test is to locate the fault to the shop replaceable unit or line replaceable unit,and then quickly complete the replacement of the fault unit to ensure the combat capability of the equipment.Based on the above background,this dissertation studies the internal structure of communication equipment from the perspective of built-in test,and designs a hardware platform of built-in test system for communication equipment fault diagnosis.The system integrates the boundary scan test mode of digital circuit and the traditional analog signal parameter measurement method.The main contents of this dissertation are as follows:1.Through the analysis of the characteristics of built-in test and the test requirements of communication equipment,and follow GJB2547A-2012 "General Requirements for Equipment Testing Work",the architecture of the built-in test system of the communication equipment is given and the overall scheme of the hardware platform is designed.2.Based on the Xilinx fully programmable SOC chip,the serial bus protocol of the BIT system and the logic circuit design of the PL terminal in the BIT main system are completed,and the communication between the main system and each test subsystem and the communication between the main system and the host computer are realized.3.For the passive test points in the test requirements,analog BITE,intermediate frequency BITE and radio frequency BITE circuits are designed.Firstly,an 8-channel ADC is used to cyclically monitor the low frequency and DC signals.Then based on the theory of band-pass sampling and quadrature demodulation,the digital down conversion and decimation filtering of the intermediate frequency modulation signal are completed in FPGA.Finally,according to the principle of equal-precision frequency measurement and TRMS power measurement method,the frequency division and detection circuit are designed,and the power and frequency of the RF signal are measured.4.Based on the IEEE1149.1 protocol standard,a digital BITE test subsystem for active test points is designed.The measurable commands covered include IDCODE,SAMPLE / PRELOAD,EXTEST,HIGHZ,etc.At the same time,the circuit under test and the scan link that can simulate the fault are designed to complete the test function verification of the boundary scan test controller of the digital module.At the end of this dissertation,the standard signal source is used to replace the test point signal in the communication equipment.At the same time,the host computer software is used to issue the test command,and the full performance index test of the designed built-in test system hardware platform is conducted.The test results show that the hardware platform can work stably and the test results of all BITE subsystems have reached the index requirements,so the design of this dissertation has reached the expected goal.