Design And Implementation Of UIPv6Stack IP Core Based On FPGA

With the approaching of the internet of things, embedded systems applications onthe network grow fast. However, the current IPv4protocol which has limited addressbits is unable to meet the huge needs of address assignment. Therefore, IPv6protocolhas become the preferred network communications, because of the128-bit addressspace, which, by the application point of view, can be considered as almost limitless.In addition, IPv6also has cured some diseases in IPv4protocol, such as end to end IPconnectivity, quality of service, security, mobility and other aspects of theimprovements. Based on the above background, and taking into account that thedesign cycle of FPGA is shorter than ASIC and the faster development, the moreconvenien validation, this project uses the FPGA-based method to achieve a reducedIPv6protocol stack IP core named uIPv6.The specific work are as follows:Firstly, the equipment needs lightweight design for IPv6protocol stack whichorient the terminal of the internet of things. By analysising and researching the basicprinciples of IPv6protocol stack and considering of the specific application, thearticle designs the lightweighted IPv6protocol, the control message protocol,neighbor discovery protocol and other major agreements.Secondly, read the IPv4protocol stack implementation and open souce code insoftware and hardware both home and abroad to understand the similarities anddifferences between hardware and software for design the protocol stack and finishthe overall of the IPv6protocol stack by hardware implementations. Then usemodular design methodology to divise the stack in accordance with the level andfunction of the uIPv6protocol stack which is already been cut, finish the design forthe interface of the model, resolve reliable transmission of the data which is crossingthe clock domain and other technical issues.Thirdly, research the IP core design technology which is based on FPGA, designand implement the core modules, build the state machine model, and write VerilogHDL code. Then use the tool which comes from Quartus II to synthesize the wholestack and analysize the result.Finally, connect each module to form a complete protocol stack system, and carryon the overall connectivity testing and performance testing, and then apply it tosubsequent experiments and work of major project named research of the generalelectric information acquision device based on IOT access technology, which comesfrom Science and Technology Commission.