Calibration Of Time Mismatches In Tiadc Based On High Speed FIR Algorithm

High speed and high precision analog-to-digital converter (ADC) has been a hotspot research field of modern digital communication system. As a link of analog anddigital domain, the performance of the ADC meet the challenge constantly.Time-Interleaved sampling technology can multiply improve ADC sampling rates andkeep the monolithic ADC precision. But it is difficult to keep the channel characteristicsthe same completely, leading to the performance of the time-interleaved ADC (TIADC)is very sensitive to the mismatch noise. With the level of digital circuit integrationimproved and the development of the theory of digital signal processing, back-enddigital calibration technology is the key to improve TIADC system performance.Back-end digital calibration technology is implementated with digital filter, highspeed parallel structure filters can be applicated in time-interleaved ADC back-enddigital calibration system artfully. Not only can solve the hardware processing speedbottleneck with the channel number increased, but provides an effective solution forhigher-frequency TIADC system.This thesis mainly includes three aspects:First of all, we analysis the blind adaptive estimation and calibration algorithm oftime mismatches in TIADC. Secondly, this paper described some high-speed FIRstructures detailedly based on the fast convolution algorithm, such as FFAS, ISCA and2-stage parallesim. Finally, an8-paralled63order high speed and high efficient filter isimplemented. The whole system works at the single channel frequency with only64multipliers used. And the back-end digital calibration system of TIADC isimplemented， followed by function simulation, STA and FPGA verification.