YHFT-DX Address Generating Unit And Data Path Physical Design

YHFT-DX DSP is designed with40nm process to achieve1GHz under the typicalconditions. The CPU core performance is the key to meet the design requirements.Based on the performance optimization of YHFT-DX CPU core, this paper has studiedthe manual semi-custom design optimization methodology on the address generatingunit circuit design and physical design. Then this paper studied the full custom,semi-custom and automatic mixed layout design methods. The main contributions ofthis paper are as follows:1）For the critical timing situation of address generating unit in the data path, thispaper investigated and accomplished manual semi-custom design methodology, whichcomprises two parts of the circuit and physical design.This paper compared therespective advantages and disadvantages of EDA tools such as DC, PT and Encounter,and the final completion of the basic processes of manual semi-custom based on a32-bitadder design.2）This paper studied the manual semi-custom circuit design method, we dividedthe address generating unit into29sub-modules by using micro architecture method,and customed these modules. We optimized these circuits by using composite gate andtri-state gate. The performance of manual semi-custom circuit design was6.7%fasterthan that of DC tool.3）This paper studied the manual semi-custom physical design method, we adoptedbit-sliced manual layout for these29modules, made each stand cell placed on thespecified location accurately. At last the custom layout area was16.85%smaller thanthe area of the tool for automatic layout. We used IPO and changing logical structures tooptimize address generating unit, which met the1GHz design requirements.4）We investigated the full custom, manual semi-custom and automatic hybridlayout design methodology in physical design. We adjusted layout of the data path, andoptimized more than110thousands um2area. We designed clock tree manually in thelocal. We used clock gating and senior metal double spacing routing to reduce the clockskew and noise.5）We used as plug repeaters, low-swing signal and regenerators in the data path ofthe global interconnect design to reduce the coupling capacitance. We also adopted setfalse path, ECO and use useful skew methods to response to timing violation, we metthe1GHz design goal ultimately.