Reseach And Application Of Low Power Consumption Scan Testing Method Of Integrated Circuits

With the increase of VLSI integration level and complexity, especially the rapid development of SoC, IC testing faces serious challenges. During IC testing, high power consumption has become an critical issue that we have to solve. ITRS(International Technology Roadmap for Semiconductor) shows that power consumption in test mode is much high than that in the functional mode. If the test power is too high, it may cause the damage of circuit structure, degradation of reliability, the decrease in yield and the increase in testing costs. In this paper, how to reduce the power consumptions(dynamic power consumption and static power consumption) during scan testing of integrated circuits is researched, the main works are as follows:1. The techniques to reduce dynamic power consumption during scan testing of integrated circuits are studied. Two techniques of gating scan clock and gating combinational logic are respectively proposed to reduce the dynamic power consumption during scan testing of integrated circuits. For the gating scan clock technique, the clock of the scanning path is modified by adding scan clock generation module, dividing the scan units in the scan chain into two paths, adding the multiplexer at scanning outputs, so that the scan clock frequency of scan chain becomes half of the testing clock frequency without the increase of whole test time, which effectively reduces the dynamic power consumption during scan testing. For the method of gating combinational logic, the combinational logic does not flip with the change of logic value of scanning units during the scan shift operation by adding the gating barrier structure, by selecting the longest key path and identifying power-sensitive scanning unit. In this way, the dynamic consumption during scan testing is reduced drastically. The combination of the two techniques is used to test ISCA’89 benchmark circuits, the results shows that the dynamic power consumption during scan testing is reduced by 43.99% compared with that conventional technique.2. The technique to reduce the static power consumption during scan testing of integrated circuits is studied. The transmission gate based technique is presented to reduce the static power consumption. The technique adopts transmission gate as the gate structure, and introduces low static power control unit, which makes the circuit produce minimal leakage current and static power consumption without increasing dynamic power consumption during scan testing. The technique is verified by a set of ISCAS’89 benchmark test circuits, and the results is compared with the prior better barrier blocking NOR technique. The results shows that the transmission gate structure has a smaller area and latency cost, and make the circuit enter a low leakage current state during scan shift mode. Thus the average static power during scan testing consumption and average power consumption during scan testing are respectively reduced by 12.34% and 6.94% compared with conventional technique.3. The methods of reducing power consumption during scan testing are applied to the scan testing design of a power line communication chip. The design of scan testing and layout of the chip are completed by DFT Compiler, TetraMAX, IC Compiler tools based on SMIC 0.18μm 1P5 M process. The results shows that testing coverage of the chip was up to 98.57%, the setup time is 2.10 ns, the hold time is 0.305 ns, dynamic power consumption and static power consumption during scan testing is respectively reduced by 37.38% and 33.87%.