| ABSTRACT:Channel coding has always been a hot research communication session, since the advent of LDPC codes, has become a hot topic of research, LDPC code parity check matrix structure with flexible, good error correction performance and low decoding complexity, decoding throughput is high. As wireless LAN technology, the development of large-capacity optical fiber, the channel in order to make more accurate information can be transmitted on the channel coding technology demanding. Today LDPC code is adopted as a standard IEEE802.11n channel coding scheme, and has been widely used in the future fourth generation OFDM communication system. This article is in the IEEE802.11n standard, using an FPGA development platform coding structure to design quasi-cyclic code. Quasi-cyclic QC-LDPC error correction codes with good performance and easy to use hardware, currently more types of LDPC decoding algorithm, this paper studies a variety of decoding algorithm based on the choice of an optimal decoding algorithm as an object of study, and developed with Xilinx FPGA chip algorithm for authentication. The main work is as follows:First, the background knowledge and the basic principles of the LDPC code and FPGA development LDPC encoding and decoding technology have been introduced. Second, after determining the parity check matrix to determine the encoding and decoding algorithms, simulation model in matlab environment, making analysis of the encoding and decoding performance, best design algorithm selected. While identifying one for FPGA design, it is in ISE14.1with verilog language development tools for coding and decoding algorithms for functional simulation algorithm design after completion of the final system will be integrated throughout the FPGA development board to do validation, the output of the decoder and decoding matlab compare the results to draw conclusions designed to achieve results showed that meet the system requirements decoder timing, resource utilization and performance. |
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