Data Encryption And Decryption Design Of AES Algorithm Based On FPGA

In the21st century, the rapid development and globalization of information has brought convenience for people. However, the hacker, trojan virus, network attacks and the other threats make information of security facing a big challenge. Government and private information will be stolen and spread, it can bring tremendous threat in people’s work and life. Therefore, the information of society will become the most important topic at present. Moreover, how to ensure the data’s security has extreme significance.AES algorithm is an encryption algorithm that proposed by the United States. Its safety, reliability is easy for data encryption, but difficult to crack. Therefore, it has been used widely in industry and government departments. The main purpose of this paper is to optimize the AES algorithm design based on the FPGA device, so that the design of data encryption and decryption system is also been done.This paper mainly discusses the basic principle and the structure of AES algorithm and analyses the algorithm and optimized the algorithm in details. It introduces the main process of data encryption and decryption realization and gives the methods and steps of designing each module. This paper proposes to use the Verilog HDL language to described the algorithm’s hardware realization and to simulate and verify AES algorithm by using QuartusII, Modelsim development environment platform.