Research On Multi-Vth Static Power Technology Based On Multi-Length Gate

In recent years, thanks to the development of integrated circuit fabrication processes, integrated circuit design methods and EDA technology developes quickly, and promotes the continuous improvement of SoC integration, making a sharp increase in power consumption per unit area, which limited the development of portable electronic products. Especially in recent years, the static power increases exponentially, even has exceeded the proportion of dynamic power in the45nm process. How to find more effective ways to reduce static power has become a big challenge for the further development of modern SoC. Since the focus of the study before we have made is mainly on the methods to reduce dynamic power, and static power optimization technology is more lacking. However, in40nm process, or even more advanced technology, we are facing urgent requirements for research on reducing static power.This thesis is based on the digital back-end physical synthesis platform Cadence encounter, from how to reduce dynamic power and static power departure, I have researched and analysed the mainstream dynamic and static power consumption reducing technology and based on the research of multi-threshold voltage static power optimization technique, proposed the method of multi-channel length technology. Through modify multi-threshold voltage technology algorithm, this thesis have combined the multi-channel technology with multi-threshold voltage static power optimization technique successfully. The main work and innovation of this paper are:1) Analyze a variety of dynamic power and static power consumption technology methods, and found multi-threshold voltage static power optimization technique have limitations;2) Analyze multi-threshold voltage static power optimization technique algorithm, and proposes multi-length channel gate method;3) Improve multi-threshold voltage static power optimization algorithm, and successfully applied multi-channel length method to multi-Vth static power optimization;4) By improving multi-threshold voltage technology algorithm based on PBA mode, improved leakage power reduction in post signoff stage.