Implementation Of1024-Point FFT Algorithm Based On FPGA

Implementation of FFT algorithm based on FPGA is the main research content in thisthesis. In this design, the signal length is1024points, the data width is24bits, the type ofmathematical operation is fixed point format, and the radix-2DIT is selected as thealgorithm. The software platform of this design is Quartus II, Modelsim and Matlab, Thehardware platform is Altera’s DE0development board, using Verilog hardware descriptionlanguage to complete the whole design.This thesis first analyzes the principle of the FFT algorithm, discussing the feature ofthe selected FFT algorithm in detail, and then gives the hardware structure of FFT based onFPGA. The main module of this design includes:data storage, butterfly unit, overflowdetecte, overflow shift and timing control. Each module’s design has a detailed descriptionin this thesis, including the core Verilog codes and the simulation results by the Modelsim.In the design validation part, in order to verify the correctness of the design preliminarilyby comparing the FFT’s simulation result of the Modelsim with the FFT’s theoretical resultof the Matlab, then download the design into the DE0development board, through theSignalTap logic analyzer to capture the FFT’s real-time data by FPGA processing andcompare by the theoretical result of the Matlab to verify the correctness of the designfurthermore. The final verification results show that the design is correct and meet therequirements.