| With the high speed development of electronic technology and the need of national electronic industry. People put forward to higher and higher requirements of performance and functions of power management chip at the same time. Miniaturization,high efficiency, anti EMI, less peripheral devices, as well as low voltage and high current power supply chip has become increasingly important subject to study. This paper is based on the development trend of the power supply demand and combining the existing research results of laboratory research, study of synchronous buck DC/DC converter chip group multiple parallel output design and implementThis paper is based on the detailed analysis of the basic working principle of buck DC/DC converter,deduction waveform on the steady of every main point has made the detailed analysis and the transmission relationship do complete. Using optimal control scheme and reduce the ripple method theoretically expounded when chips parallel, After that design a synchronous buck converter with a low ripple rate and multiplex parallel output. Converter with peak current mode PWM modulation control method, which can improve the transient response speed of the system and has the advantages of small output inductor, at the same time the compensation circuit is simple and the gain bandwidth is wide and is easy to current sharing. This chip can realize single channel with high current and paragraph two chips in parallel in double channel.The output can even use more chips in parallel to achieve greater current. In order to reduce heat loss requirements and the reaction speed improvement of the system, improve the system reaction rate, prolong the sub module in chip group life. We should take full account of the multiple DC/DC converters in parallel realizing current sharing between both chips at the same time. The chip introduced PLL circuit and a divider circuit, which can reduce large capacity in multiphase model, at the same time under high current work it still has a smaller input and output voltage ripple. And integrated PLL master-slave module synchronization and by setting method of current sharing control mode.the effective control of the chip parallel output, realizing output current sharing. When working in light load, we can choose two different ways of working methods: forced pulse width modulation(FCCM) mode or pulse skip modulation mode(PSM) from the output voltage ripple size and efficiency according to customer needs. As to wide inputand wide output range of the chip, a squarer slope compensation technique is presented to application in, compared with a linear slope compensation, further improve the carrying capacity of the whole chip and the elimination of the duty ratio greater than50% appeared when the sub harmonic oscillation, open-loop unstable and sensitive to noise and other short comings. At the same time it is adopted in the design of dynamic clamping circuit, the output of the error amp uses dynamic clamp, relative to the fixed clamp voltage, can effectively avoid the influence of slope compensation on the chip with a carrying capacity of. In addition, the chip also integrates the function of under voltage protection、over-voltage protection、over-current protection and external soft start circuit etc.According to chip work efficiency the paper selection and effect of chip peripheral devices also make detailed analysis, but also the cause of the chip selection of BCD technology is explained.This paper research on multi-channel parallel flow buck DC/DC converter chip group with a 0.35 um BCD process design. compeleted the core film module and the overall function simulation in Cadence. A single chip input voltage ranges from 4.5V to 26.5V,the largest single channel 8A can pull the load current, and can achieve more than 12 chips in parallel, so the output current can be as high as 96 A, single chip efficiency can reach 95%, meet the design requirements. |
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