Design And Implementation Of PXIE High-speed Interface In Real Time Signal Analyzer

Real-time signal analyzer is widely used in wireless communication、aerospace、 navigation and other fields as a test instrument. Digitization, broadband and high resolution ratio have become the trend of real-time signal analyzer, which requires data transfer bus has great bandwidth, high stability and reliability. Nowadays PXIE(PCI Express eXtensions for Instruction) has turned into the mainstream technology of instrument bus, the rate of PCI Express v2.0 reaches up to 5.0Gb/s, PCIE differential serial transmission and error correcting mechanism ensure transmission quality.In order to meet the need of massive data transmission of real-time signal analyzer, this thesis discusses PXIE bus technology. First of all it needs deep understanding of PXIE hardware specifications and PCIE transport protocols for fulfilling the design. This thesis completes overall program design of PXIE high-speed interface based on requirement analysis, designs hardware implementation which uses FPGA as the main device based on the implementation of PXIE, designs the logic frame of PXIE transport protocol、DMA controller and high-speed cache for high-speed data transmission, accomplishes circuit design in detail by Cadence software depending on the hardware implementation(the main considerations of circuit design are system performance, power and integration), completes detail logic design and RTL level code of the PXIE transport protocol、DMA controller and high-speed cache depending on the logic frame with ISE14.2 software. The most important of the thesis is designing the DMA controller and high-speed cache. This thesis accomplishes the implementation of PIO, DMA and interrupt data transmission. FIFO、RAM and DDR3 three ways are used to cache different types of data.Logic debugging platform is built after debugging the hardware of the board. Chipscope software of Xilinx ISE14.2 is used to debug and verify the logic design, which includes PIO、DMA read、DMA write and interrupt. DMA read transfer rates reaches up to 5.78 Gb/s, DMA write transfer rate reaches up to 13.33 Gb/s, Interrupt singal works properly. It turns out that the result of debugging and verification matches the logic design and Satisfies the desired performance. In other words, it indicates that program design, hardware and FPGA logic is correct. High-speed interface hardware and logic design of this article has been successfully applied to real-time signal analyzer.