Research And Design Of The High Efficiency, Synchronous Multiphase Switch Controller

With the rapid development of electrical equipment for industrial and medical equipment, computer systems and telecommunications system, the demand of their power is increasingly high. The power supply of high load current must have higher efficiency.A high efficiency, multi-phase, dual channel, selectable switching frequency(250 kHz-770 kHz) synchronous rectifier which is suitable for high current output, is designed.This paper first introduces BUCK DC/DC converter power loss, including conduction losses, power MOS switching loss and gate driving loss. we pay the loss for the modeling, the big electric load shedding more precise mathematical model. Analyze the various factors influencing the gate drive loss, laid the foundation for subsequent high efficiency of the converter design. Then the proposed method can reduce the converter power loss in turn. Through the adoption of DCR test, effectively reduce the power loss of the conduction process. The application of multiple phase makes the output capacitance of the power ripple and RMS of input capacitance current is much less than multi-phase mode. With the decrease of the input and output capacitance, greatly reduce the losses. because the clock delay is less, multiphase application has a single output faster load step response. low impedance gate drive provide larger average drive current, maximum shortening the switching time of the power tube, reduces the power tube switching process of the loss, improve the efficiency of the converter. In addition, the optimization design of the secondary power supply fully meets the current needs of the drive, effectively reduce the switching loss in the process of driver.We use CSMC / 40 V BCD process and Cadence and HSPICE simulation tool for chip internal module and overall performance simulation. The results showed that high efficiency design techniques improve the efficiency of the converter up to 93.6 %. The overall electrical characteristics simulation results show that the chip meet the design requirements.