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Design And Implementation Of Multi-Mode High-Efficiency Synchronous BUCK DC/DC Converter

Posted on:2008-09-20Degree:MasterType:Thesis
Country:ChinaCandidate:Z H ZhuFull Text:PDF
GTID:2132360212478428Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
The paper is based on the project "Theoretical research and design of key technique for power management IC", and it mainly studies the design and implementation of BiCMOS DC/DC converters. Through systematic design, circuit design, layout design and performance simulation, a multi-mode high-efficiency buck converter, named XD9033, is introduced in this paper.This paper analyses and studies the basic principles of buck DC/DC converter which is the theory guidance of the design and implementation of XD9033. As a result of adoption of current-mode control, the transient response speed of the supply voltage and the load variety become faster; in order to overcome the disadvantages of current-mode control when the duty cycle is greater than 0.5, such as instability of open-loop, sub-harmonic oscillation, non-ideal loop response and an increased sensitivity to noise, a piecewise linear slope compensation circuit is designed; furthermore applying a phase-lock loop to the chip realizes the function of outer synchronization, which is helpful to reduce the interference from other power supplies in the distributed power system, the frequency capture range is from 1.1 MHz to 1.9MHz; pulse skipping mode or burst mode can be selected according to the circumstance, in addition, lots of protection circuits are integrated in the chip, such as over current protection, thermal shutdown, and so on.Also, this paper deeply analyses and studies the layout design of switching converter and annotates the key factors that should be considered in layout design. At last, the layout of XD9033 is schemed out based on 0.6μm BiCMOS process, and it passes the DRC and LVS verification. Then the post simulation is carried out and the results show that all of the electrical characteristics can meet the specifications. For instance, the efficiency is up to 96%, the quiescent current of this chip is only 10μA during operation, and drops below 1μA in shutdown mode. The design project has passed the acceptance check and taped out, now the chip is being tested.
Keywords/Search Tags:Converter, Current-Mode, Slope Compensation, Phase-lock Loop
PDF Full Text Request
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