Research On FADEC Interface Emulation Technology With High Confidence

In the increasingly complex development of Full Authority Digital Electronic Control(FADEC) system process, it has become an efficient and inevitable trend to conduct a comprehensive test verification on control system by HIL(Hardware-In-the-Loop) simulation and Semi-Physical simulation, and FADEC system interface emulator is the key of the test verification. In this paper, aiming to develop a compact FADEC system interface emulator with high degree of confidence, the following studies have been carried out:1. Overall design of FADEC system interface emulator. The mathematical models of various interfaces were built based on the working mechanism, dynamic and static characteristics of typical sensors and actuators in aero-engine control system. The mathematical models were the basis of hardware and software designs in the interface emulator. Aming at the poor openness and big volume of conventional interface emulators, a compact interface emulator based on NI c RIO was proposed.2. Circuit design of interface emulator. The interface analog circuits of speed sensor, pressure sensor, temperature sensor, displacement sensor and servo valve were designed based on the interface mathematical models. The analog circuit of speed sensor was mainly researched, and a speed sensor signal simulation method based on the dual digital signal synthesis technology(double DDS) was put forward. With the arbitrary waveform simulation capability and the improving of frequency simulation accuracy, this method has solved the problem of the speed sensor fault simulation.3. Software design of interface emulator. An integrated FADEC interface emulator configuration and management software(FIECM) was designed based on Labview. The basic function of FIECM was to control the dynamic behavior of sensors and actuators, and control the interface circuits by running real-time models in c RIO. FIECM also included the channel calibration and verification software based on the least square method, and the signal monitoring and management software. It also provided the communication interface with engine model programs so as to facilitate Hardware-In-the-Loop simulation and Semi-Physical simulation.4. Testing and simulation verification for FADEC system interface emulator. The emulator’s static characteristics were tested through the channel calibration and verification software. The results showed that the modules’ accuracy was better than 0.5%, the signal update time was less than 1ms. The emulator’s dynamic characteristics were tested through the Hardware-In-the-Loop simulation of controllers. The coordination work between the interface emulator and the electronic controller has completed the small needle position loop control test and the closed-loop speed control test. The results have verified the dynamic interface simulation capabilities of FADEC system interface emulator. Finally, the waveform distortion simulation of speed signal was also tested.