The Design And Research Of 10kV Transmission Line Traveling Wave Fault Location Device Based On FPGA

With the rapid development of integrated circuit and microelectronic technology, many kinds of travelling wave fault location algorithms are implemented on the high performance hardware. Many manufacturers researched and developed traveling wave fault location devices for high voltage transmission lines and power cables, however, due to the railway 10 kV transmission line neutral point non-effectively grounded, fault signal is generated particularly weak when a ground fault occurs, and there are not only mixed line but also many branches, because of many interference and complex factors, the actual detection are particularly vulnerable to error detection, leak detection and low precision situation. High voltage traveling wave fault location devices is not fully applicable to 10 kV lines.FPGA has the advantages of high-speed and parallel, flexible and programmable, and also has short development cycle. Therefore, it is of important and great significance that designing 10 kV transmission line traveling wave fault location device which is based on a set of FPGA devices, to protect safe and reliable operation of 10 k V transmission line, and to improve the accuracy of fault location,In this paper, the principles and implement of fault location is studied for 10 kV small current grounding system fault characteristics, traveling wave fault location device based on FPGA is designed. The main work and research results are as follows:Firstly, MATLAB / Simulink library of PSB established simulation model of fault features 10 kV small current grounding system was analog and simulated to get the transient traveling wave fault signal generated instantly.Secondly, the internal logic circuit of traveling wave fault location hardware devices were designed, including the global clock management, AD transformation, Phase-modulus transformation, wavelet filtering, fault distance calculation, SDRAM high-capacity storage, and different clock FIFO interface circuitry.Finally, timing simulation and board-level testing were done for the functional modules of the designed device,test results show that, the FPGA hardware device timing designed is stable, and have higher accuracy.