High-speed Multi-channel EEG Acquisition System Design And Research On Data Compression Algorithm

EEG is the group of spontaneous electrical activity of brain cells in human body, and it is rich in the human body physiological and pathological information. With the rapid development of the brain electrical signal processing technology, a kind of equipment used for recording the electrical activity of the brain wave, namely the electroencephalogram (EEG), has been widely used in brain science, virtual reality technology research in the field of BCI system, biological feedback therapy apparatus, especially in epilepsy, intracranial space-occupying lesions in the clinical diagnosis of brain disease has an in-eplaceable role. Domestic EEG acquisition system comparing with abroad EEG acquisition system, has the following disadvantages:weak anti-interference ability, narrow band waveform distortion, etc., so the study of independent property rights of high levels of EEG acquisition system is of great significance.Because μV brain signal is very weak, the key problem of μV brain signal acquisition is restrain outside interference effectively on the premise of guarantee high signal gain. In this paper, we design a high input impedance, high common mode rejection ratio, low noise and low drift signal amplifier, and adopt the unique "three average public potential+digital differential" technology, photoelectric isolation and complete electromagnetic interference shielding technology, which can realize wideband undistortde amplification of μV EEG without hardware power frequency trap, and use the way of high-speed AD, high-speed multi-channel electronic switch with sampling keeping circuit to realize high speed synchronous sampling.Because on traditional dual control of EEG acquisition system, ARM and FPGA and SDRAM communication process is repeated and Small on data throughput and low on transmission efficiency, we design a high-speed multi-channel EEG acquisition and transmission system, which is controlled by FPGA and ARM. On the scheme, FPGA control external cache SDRAM, and it can realize reading and writing at the same time on asynchronous clock by SDRAM and the ping-pong operation of FIFO, it make the FPGA and ARM joints data uninterrupted, and realize efficient communication on FPGA and ARM through the simple parallel interface protocol, for the ARM, FPGA and SDRAM completely equivalent to a SDRAM, which can collect data automatically. In the end, the ARM will apply the high-speed data to the liquid crystal display, or sent it to the PC via Ethernet.Considering the EEG acquisition system will collect EEG data for a long period of time, EEG data increased quickly, and embedded systems have not much space to store a large amount of data, this paper proposes a method for 2 d image compression, and applies the algorithm on one-dimensional compression of EEG after modified successfully. Then aiming at the shortcomings of EZW coding algorithm, we design a kind of improved compression algorithm based on EZW.In this paper, we verify the design of EEG acquisition system, test results indicate that each index of the system is good, and it can meet the needs of the clinical application. Through the simulation of EZW algorithm and improved EZW algorithm, results indicate that EZW algorithm is able to real-time compression EEG data effectively, and the improved algorithm can achieve higher compression ratio and reconstructed signals of higher quality.