The Reascher And Implementation Of The Typical Parts Of Remote Sensing Image Compression Algorithm Based On JPEGXR

With the rapid development and popularization of Multimedia technologyand Wireless communication technology，people are eager to acquire more image.At present, the size of image are always big, so there is a challenge for the limitof channel transmission bandwidth and storage space. Image compress ion is aneffective way to solve this contradiction.Now there are three static imagecompression international standard and JPEG XR is the latest.Compared to JPEGthat is most widely used，JPEG XR over the deficit of block artifacts at low bitrate and improve the quality of image.JPEG XR can almost get the same qualityof image that compressed with JPEG2000，but the source consumption is veryclose to JPEG. Because of its low Complexity of the algorithm.Therefore, JPEGXR has much more research value for compression equipment that are onsatellite and other devices that have fewer source.The devices that processed Image data are generally require highthroughput.so,the FPGA is a good choice for its powerful parallel processingcapabilities.At first，The paper studies the typical parts of the JPEG XR imagecompression standard such as Image pre-filtering,Image Core transform,Quantify,Predictive Coding and so on,and then the theory of these parts are reached indetail.Secondly，these parts become specific modules through programming withVHDL language and these modules are internally designed in pipelinedmanner.In order to make sure that these modules can achieve its correspondingfunction, we need to do TRL simulation through modelsim software. To achieveits function completely, the typical part encoder of JPEG XR design threepipelining to make these module to become a whole. Under the control of thefirst line, image data are read and pre filtering and then perform image coretransform and quantity under the control of the second line,finally, imageprediction encoding are carried on in the third pipelining. At last, the encoderdesigned is simulated at100MHz of input frequency through Modesim10.1d andthe compressed stream can be displayed properly in computer with Win7system.The encoding rate is0.326pixel/cycle in simulation. The typical parts of encoderare tested on the FPGA hardware platform base on EP2S130F1020I4.In thepractical circuit, the typical part of the encoder can work no rmally under the100MHz input clock frequency.The actual encoding speed is faster than simulation,which can up to0.437pixel/cycle.