FPGA Implementation For QC-LDPC Decoder And Its Application In Network-coding System

Since be rediscovered in1990s, because of great error correction capability which approachingShannon limit and advantage of low decoding complexity and high decoding throughput, LDPC codeshave attracted people’s attention. Now LDPC codes have being widely used in many mobilecommunication systems such as DVB-S2, CMMB and Wi-Fi.With the development of research onLDPC codes, the implementation of LDPC codes on hardware also has high-speed development. Atthe early stage, implementation architectures of most decoders for LDPC codes are serial architectureor parallel architecture. But both two architectures have obvious disadvantages. After QC-LDPCcodes being raised, semi-parallel architecture have being more and more used. Semi-parallelarchitecture archives a balance between decoding throughput and hardware resources consumption.This thesis is organized as follows:1. In order to understand the LDPC code deeply, firstly we review the linear block codes andShannon coding theorem simply，then do some simulation comparison for the performanceimpact factor. We also introduce the basic knowledge of LDPC codes and the encoding methodand the encoder structure. Lastly we propose the concept of QC-LDPC codes and analyze theshort cycled impact on its performance, mainly introduce the construction method with big girthnumber which is based on sub matrix shift algorithm.2. We discuss and analyze several kinds of soft-decision decoding algorithms. We compare theerror-correction performance of several kinds of soft-decision decoding algorithms. Finally,Normalized Min-Sum algorithm is chosen for hardware implementation. Meanwhile, throughsoftware simulation, modified factor0.75is recommended and quantitative setting with6bits.3. We analyze the structure about cooperative communication system and introduce three methodsof cooperative. Then we take out the related knowledge of network coding and introduce twokinds of network coding combined with cooperative communication system based on networkcoding conception. We are focused on network coding cooperative communication system basedon LDPC codes, from the codes designing to the MSA iterative decoding based on joint Tannergraph, finally make a relevant performance simulation analysis.4. After introducing the structure of the overall decoder and each sub-module and accomplishing thedesign of the decoder using Verilog language, the decoder using FPGA devices EP4SGX230KF40C4ES is compiled by Quartus Ⅱand simulated by Modelsim. The simulationresult shows that the improved check-module can conquer redundant iteration and improve thehardware resource utilization. When the clock frequency is86MHz, the throughput can reach88.62Mbps.