The Encoder Design And Implementation Of CCSDS-Based Low Rate LDPC Codes

Channel coding technology provides effective and reliable protection to digital communications systems. As a channel coding scheme, low-density parity check(LDPC) codes has now closest to the Shannon limit performance. An encoder architecture is proposed to implement 1/2, 2/3, 4/5 rates LDPC codes based on the Consultative Committee for Space Data Systems standards. According to block cycle characteristics of the generation matrix, it used a feedback shift register design this encoder for saving hardware cost. And it add zeros at the end of information to ensure the stability of the LDPC code encoder.Firstly, this paper studies a LDPC codes constructed by protograph, especially an AR4 JA protograph LDPC code. The structure of the parity check matrix and the generator matrix is described in details. The decoding performance of AR4 JA is analyzed by DE theoretical analysis and EXIT charts. Also, the CCSDS standard used AR4 JA protograph to construct LDPC codes, it provide a method for constructing a parity check matrix, and a detailed analysis of CCSDS standard encoding method.Secondly, the paper contrived the quasi-cyclic codes coding method. The generator matrix solved with the CCSDS standard has the system characteristics and quasi-cycle characteristics. According to its characteristics, a coding circuit based on a feedback shift register accumulator has been proposed which has low complexity and less hardware resources.Finally, An encoder design of LDPC code based on CCSDS standards is proposed. The data packet completes data framing operation, the add zeros at the last of data frame to ensure that the output codes have same size with the input information, thus this operation can make continuous coding accuracy and stability. Depending on the occasions, it proposed serial and parallel encoding circuit. Also, it verified that FPGA coding is correct. Through simulation software coding and decoding performance curve analysis, compared with the decoding performance given by the CCSDS standard. Then the hardware and software coding result of the coding results were compared to verify the correctness of FPGA coding.