Implementation Of Code Generation For MIPS Processor And Research Of Related Optimization Technology

MIPS which means Microprocessor without Interlocked Pipeline Stages, is a very popular RISCprocessor in the world. Compared with CISC, the clock cycle of RISC is generally shorter with thesimpler design, and RISC can utilize more advanced technology to develop more efficientnext-generation processors.Without the bootstrapping capability, MIPS processors always request a cross-platformdevelopment environment. And for special requirements including low power needs, fast runningspeed and compact code, it requires designers to design efficient application software and compilersto be capable of enough optimizations. Secondly, there are many kinds of MIPS processors, whichdemands the compiler should be easy to retarget in order to support the software development for thenew processor platform.This thesis describes porting the LCC targeted for the32-bit MIPS processor and theoptimization on the back end at the heart, and analyzes in detail the overall structure of the LCC andthe characteristics of MIPS architecture. According to special requirements of embedded systemdevelopment, the thesis makes improvements on the code generator, designs and implements theassembler, and studies the optimization for assembly code for the subset of32-bit MIPS processors.The main work of this thesis is generalized as follows:(1) Explore current mainstream compilers in depth, and choose the LCC compiler as researchobject;(2) Modify machine description on LCC targeted for the MIPS in order to meet the requirementof the subset of32-bit MIPS processor’s instruction set, and use the LBURG tool to build codegenerator for generating MIPS assembly program;(3) Analyze the typical assembler with single pass, design and implement a two-pass assemblerwhich translates the MIPS assembly program into machine language program;(4) Analyze and summarize existing optimization strategies and specific implementationmethods in compiling stages, and work out optimization schemes for the MIPS assembly program;(5) Study a32-bit three-stage pipelined MIPS processor and simulate it through ISE.Finally, the PCSPIM and ISim (ISE Simulator) tool built in ISE are respectively used to dofunctional testing and verification for the improved code generator and implemented assembler, whichshows that the code generator and assembler are in line with the design object.