Research On Functional Verification Based On Wireless Communication SoC Chip

With the increasing of the scale, complexity and functionality of the SoC (System on Chip) designs, the time grows at a double-exponential rate during the verification process, also, more and more resource cost at verification phase which make the traditional verification methods are no longer to meet the needs of verification. The huge pressure of validation force verification engineers to break through the traditional methods and develop the new verification technology to improve verification efficiency and shorten project development cycle.SystemVerilog introduces object-oriented programming approach, has gradually become a major validation of large-scale circuits using language. The Verification Methodology Manual (VMM) based on SystemVerilog which consists of methodology guidelines and a range of standard library, also has the feature of SV language supporting random test, automatic compare and coverage-driven. These are all made the structure of verification environment more simple and standardized. Based on these methodology guidelines and class library, it is easily to construct a reusable verification environment, making verification efficiency has greatly improved.In this dissertation, under the background of wireless communication SoC transceiver chip, firstly, the system’s overall design, structure have been analysed deeply, then formulate the strategies and technological processes of verification, and complete the building of the SoC verification platform based on VMM. At the same time, a coverage-driven combined method of assertion verification has been introduced to the platform and controls the progress of verification by means of analyzing code coverage, functional coverage and assertion coverage, at last the code coverage reaches99.73%, the functional and assertion coverage reaches100%. Verification results show that the verification environment designed for wireless communication system has a clearness arrangement and a better reusability, also can be easily automated. The rational use of verification platform can save time greatly of debugging, shorten the verification cycles and accelerate the development process of the project, the entire verification process fully reflect the use VMM verification methodology advantage.