DVB-S Channel Decoding And Implementation Based On FPGA

DVB-S satellite broadcasting system is widely used in the world, in order to improve the anti-jamming capability, guaranteed transmission reliability, the system uses FEC channel coding. The channel coding is a kind of concatenated code which takes the RS code as outer code and the convolutional code as inner code, has very strong error-correcting capability. Therefore, research on DVB-S channel code and decode is of great significance for target reconnaissance and jamming of communication subjects aiming at DVB-S satellite broadcast.This paper first describes the DVB-s channel coding protocols, and designes a decoding method on the basis of researching on theory of FEC coding and decoding and the technology of interleaving. In the programme, mainly consists of6modules: phase de-ambiguity, Convolution decoding, frame synchronization, deinterleaving, RS decoding, derandomization, and describes the working principle of each module in detail. The subject takes Xilinx Corporation Virtex-4series FPGA as the development platform, useing ISE software to achieve the decoder in FPGA design, simulate functions by Modelsim. Finally, the design is validated on hardware platform, the experimental result indicated that the decoder working stability with good performance.