Low-power Oriented Research Of Multi-core And Multi-threaded Architecture

Sustainable development of manufacturing technology provides an exponentialgrowth of available transistors for chips, and a single chip can even accommodate onebillion transistors. Consequent energy consumption and heat density become themajor bottlenecks that limit the processor’s performance. How to utilize this kind oftransistors resources, and how to convert them into relatively effective computingability that adapts to future applications have become the new research problem.Compared to switching delay, line delay increasing constantly, and heat density alsoapproximates the chip cooling ultimate. While the line complexity makes a simpleaddition to the existing processor design vanish into thin air, designers have toabandon the traditional methods that increasing system performance by increasing thesingle-chip performance, and turn to multi-core architecture to enhance theprocessor’s performance. Previous studies have indicated that there is a greatdifference for the need of resources of different applications, and significant benefitscan be obtained through resource reconfiguration. This paper has a in-depth researchon dynamic resource management technology based on multi-core multi-threadedarchitecture. Major works are as followed:With reading the literatures and related technical documents written by theexperts in the multi-core multi-threading field, this paper have done a systematicanalysis and elaboration on CMP, SMT, fine/coarse-grained multithreading and thekey issues need to be solved, as well as the pros and cons of the various architectures.In an real processor product, it does not use a single processing structure usually, andusing a variety of architectures mixed to reach the optimal match of processor,multi-level Cache and storage. Basis on the current structure of commercialprocessors, the writer believes that the hybrid architecture of CMP and SMT would beoccupying the mainstream position in a very long time.Currently, there are several resource re-allocation algorithms in SMT: usingL1/L2Cache miss rate or IPC as the indicator, control the allocation of data pathresource between different threads; Or through a variety of allocation scheme testing,track the optimal resource allocation of the system requirements dynamically. Thesetwo kinds of allocation algorithms either have little correlation with the target or takea long time before finding the best scheme. This paper proposes the resourceutilization as the measurement indicator, set resources absorption wall at the sametime to prevent the thread from starvation. Most of the resources dynamic management in-core limited in SMT processor,since SMT has low scalability and it is often unsatisfactory to transplant this approachto other architectures directly. This paper presents a dynamic resource managementalgorithm based on CMT architecture, which can dynamically adjust the resourceallocation of several threads. Under the premise of stable performance considerclosing redundant resources to achieve the purpose of energy saving. Also considerthe impact of multicore multi-threaded structure on the overall system throughput. Inorder to verify the dynamic reconfiguration scheme proposed in this paper moreaccurately, I use Simics+GEMS to simulate the full system SPARC platform andvalidate the result using SPEC OMP benchmarks. The results show that in the fourcores with four threaded environment, compared to conventional static partitioningscheme, my solution reduces18.13%power, and have40.1%performance increase.