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Research Of Visual Information Pre-Processing Sub-System Based On Reconfigurable Processor

Posted on:2015-07-23Degree:MasterType:Thesis
Country:ChinaCandidate:L WangFull Text:PDF
GTID:2298330452458980Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the fast development of multimedia technology and digital image technology,standard definition (SD), high definition (HD) and even ultrahigh definition videoquickly gained popularity. Bringing clearer picture quality and visual enjoyment, theamount of data and computation complexity in visual information processing has alsoincreased sharply at the same time. Compared with traditional processor,reconfigurable processor can achieve the higher calculation efficiency, so as toeffectively solve the above problem, and it has become a new research focus in thefield of visual information processing.This thesis introduces the architecture of the visual information system based onreconfigurable processor and analyses the data flow in pre-processing sub-system.Then modules of the pre-processing sub-system are designed as follows: the imagesensor was configured by SCCB to make the image sensor output specific imageformat and image size. A median filter circuit was designed to eliminate impulse noisein the image and to reduce the impact of noise on corner detection, image mosaic andother advanced image processing algorithm. A DDR controller was designed to realizeimage frame caching in the DDR memory. To realize communication betweenpreprocessing system and reconfigurable processor, this thesis defined acommunication protocol between them. The whole system was controlled byMicroblaze, a processor core supported by Xilinx to complete system initialization,function change, format verification and data flow control. This thesis also proposed aweighted vector median filter based on edge detection to protect image details whenfiltering the color image.All the circuits designed in this thesis was simulated on Modelsim and verified on theplatform of LX110T. The OV2640chip of OmniVision was used as the HD imagedata source. Experimental results show that the system can correctly receive imagedata and the whole system can work in a right way. Simulation results on Matlabshow that the proposed VMF algorithm outperforms all algorithms examined in thisthesis in terms of MAE, MSE and PSNR values. Statistical results show that thePSNR values increased by7.2%compared with standard VMF algorithm.
Keywords/Search Tags:Visual Information Processing, Image Denoising, Median Filter, Reconfigurable Processor
PDF Full Text Request
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