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Research On Architecture Of Visual Processing SOPC Based On Reconfigurable Processor

Posted on:2018-12-29Degree:MasterType:Thesis
Country:ChinaCandidate:K X ChenFull Text:PDF
GTID:2348330542481085Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the rapid development of visual information processing technology in various industrial fields,high-resolution video technology attracts significant attention in recent years.Due to the large amount of image data and high-throughput performance requirement,the design of visual information processing system is becoming more and more complex.Among traditional methods,because of inefficient computation of General Purpose Processor and poor flexibility of ASIC,they are hard to meet the needs of high performance and flexibility.With the help of flexibility of software,performance of hardware,and capability of parallel processing,reconfigurable processor has become a new research hotspot in the field of visual information processing.This thesis focuses on the research of architecture of the visual information processing SOPC based on reconfigurable processor,the storage unit is efficiently utilized and the design and verification of interfaces between sub-systems are completed with the help of the arbitration of the access mode.It ensures the stable transmission of video image data in real-time visual information processing system.Firstly,an interface unit between the main processing sub-system and the post processing sub-system is designed to complete the transmission of visual information after image mosaic,and an interface unit between the post processing sub-system and the display device is designed to display videos in a standard format.Then in the parameter transmission and control interface unit,a transport protocol based on UART is established.And frame conversion unit is designed in the off-chip memory interface to ensure the stability of video streams.In the interface to reconfigurable processor,various design methods of different types of asynchronous signals are compared and implemented.In addition,to make an effective and timely evaluation of the image quality during the design of the visual information processing system,in this thesis,a novel perceptual image quality assessment metric based on global and double-random window similarity is proposed.Compared with 11 state-of-the-art image quality assessment models on 4 most widely used large-scale benchmark databases,experimental results show that the proposed method in this thesis has a much better performance on the prediction accuracy with a low computational complexity.The correctness and robustness of the architecture in this thesis are proved with the help of the simulation and verification results from software and hardware.Interfaces between sub-systems and reconfigurable processor are proved to support the transmission of image data and parameter signals,the visual information after image mosaic can be displayed in a standard format in the real-time system,and registers can be dynamically configured to switch the mode in the flexible system.
Keywords/Search Tags:Reconfigurable processor, Buffer planning, Asynchronous design, Image quality assessment
PDF Full Text Request
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