Studyand Implementation Of ADPCM Speech Coder And Decoder On FPGA

With the microelectronics and computer technology’s rapid development, the digitalsystem design technology has also had rapid development. The emergence of large-scaleprogrammable logic devices and the development of integrated technology, promotes theconcept of digital system design profound changes. Today most of the digital signalprocessing using DSP or ASIC of the program. It has the following problems: badlyhigh-speed performance, long development cycle and high cost and so on. Now we useFPGA to process digital voice signal at real-time. It can not only increase the processingspeed, making the system easier to maintain and upgrade, and effectively shorten thedevelopment cycle and reduce development costs.This thesis mainly studies the ADPCM speech decoding algorithm and software andhardware scheme based on FPGA implementation. ADPCM is a algorithm of16bit widthof the PCM voice signal, it effectively reduces the storage space, can expand the channelcapacity in communication. According to the characteristics of the algorithm, this paperchose the XC3S1000of Xilinx’s Spartan3series which is the core chip of the system.Development environment for ISE, in this platform complete each module using VerilogHDL language. For example, UART serial transceiver module codec module FIFO buffermodule, etc. Using simulation tools Modelsim simulation on the functions of the variousmodules, verify the logic function of each module. In order to further verify thefunctionality, but also set up the hardware circuit, Include: load FPGA circuit, powersupply circuit, DA conversion circuit, interface circuit and so on. It completed for thevalidation of the actual hardware circuit design of digital system.After a software simulation and hardware verification, proving that FPGA designdigital voice processing systems has obtained a better codec effect. It fully embodies thegood real-time, maintenance convenience and low cost advantages. In addition, you canfurther improve the FPGA design, to develop it into IP core, make its application moreconvenient.