The IC Implementation Of MJPEG Video Decoder Based On FPGA

With the continuous development of science and technology, a variety of multimedia technology have been widely applied to the Internet and our daily lives. Among these stardards, JPEG has been widely used in the field of digital image processing for its excellent performance. It allows to store and transfer digital image data with considerably reduced damand for storage space and bandwidth. From the four processes provided in the JPEG standard, only one, the baseline process in widly used.In this thesis, it first briefly introduces the JPEG standard and JFIF(JPEG File Interchange Format). And then elaborates the algorithms of all the major parts of JPEG baseline process in detail. After compare and measure these algorithms, a hardware based system to decode JPEG baseline compressed image data is presented, and the different stages of the decoding process are implemented in a pipelined design described in Verilog HDL. It is also with the simulation waveforms and the implementing result of JPEG decoder. The decoder can decode multiple JPEG images simultaneously for the pipelined architecture. Thus, it is especially suited to decode MotionJPEG movies. In the last part of the thesis, based on the JPEG decoder, a MJPEG decoder design is raised and complete the functional simulation and FPGA hardware verification which ensure accuracy of the design.The design and implementation of JPEG baseline decoder provides an active exploring to designs of other more complex image decoders and encoders and the design of MJPEG video decoder brings a positive reference to implemente the decoders of varied multimedia.