Research And Design Of Phase Locked Loop On High Speed Interface

Nowadays high-speed interface system design needs clock to make the operation of functional modules synchronous in the system and determine the communication protocol among different systems. As a basic module in high-speed interface system, phase locked loop provides different frequency and performance indexes clock for the entire system.A phase locked loop has been designed in this paper, taking HDMI2.0 interface standard for example. Based on CSMC 0.18um CMOS technology, the input clock signals generates eight equidistant 25MHz-600MHz clock by the phase locked loop circuit.The principle of phase locked loop has been studied. And the phase locked loop modules have been designed by Cadence software, including phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, frequency divider and LDO circuit. Delay unit has been added considering the dead zone problem when designing the phase frequency detector. Current steering charge pump has been used to improve the charge sharing effect, which consists of two complementary switches and a unity gain operational amplifier. Four-stage differential ring voltage-controlled oscillator has been designed in order to meet the requirements of eight equidistant clock. A ten frequency divider formed by a high-speed TSPC two frequency divider and a cascade five frequency divider has been designed. Since phase locked loop is sensitive to power fluctuation, LDO has been used to provide pure and stable supply voltage for the other modules, converting the 3.3V input supply voltage into 1.8V stable output voltage. And the simulation results show that the phase locked loop circuit designed in this paper can realize the expected function. Based on the latest HDMI2.0 standard, this PLL circuit is good for application and research.