The System-level Verification For Smart Card Based On VMM

With the rapid development of So C(System on Chip) technique and the widely use of IP(Intellectual Property), chips are becoming more and more integrated and complex, the risk of mistakes in IC design is getting higher and higher. Verification technique provides an effective way to find out functional errors of So C chips. Research shows that the workload of verification has occupied more than a half of time and labors in the whole process of chips’ design. And verification has become an obstacle of shortening the IC design cycle. The importance of verification can’t be ignored.In this paper the functional verification of digital So C was studied. First, the development of So C is surveyed, showing the importance of verification in So C design. Besides, the difficulty of verification is learned. After analyzing and concluding various verification techniques, methods and languages, the methods to improve verification efficiency are shown. The verification language system verilog possesses many features which directly connect with verification, such as OOP(object-oriented programming), constrained randomization and function coverage, therefore abstract models of systematic structure levels can be built with it, providing strong support for the system-level verification. The verification methodology of VMM provides a standard library, making the establishment of verification testbench easier. What’s more, with the strong capability of dealing with texts, scripting language promotes the automation of verification process, reducing plenty of work.Smart Card chip is a typical SOC. The functional verification of the Smart chip is realized in this paper. First, an architecture verification flow, from module to system, is proposed. Then the ISO / IEC14443 protocol and the ISO / IEC7816 protocol which are used in Smart Card are studied. In addition, the principles of RF module and 7816 module are researched. Based on VMM, a reusable and configurable testbench for RF module and 7816 module is built, achieving coverage-driven block level verification. For the feature that system level verification focuses on the real implementation scenarios, a system level testbench consisting of the reusable block level testbench is built with C software based on the ARM programming. To achieve the automation of verification, a lot of scripts are developed in this project to simplify the whole processof verification.In summary, an efficient and useful method was proposed for So C system level functional verification in this paper. First of all, to build block level testbench which is reusable and configurable is essential. Then a testbench consisting of the reusable block level testbench and C sofetware testcase can be constructed. Last but not least, scripts should be written, which run the simulation and compares the result of simulation. The feasibility of this verification method is tested through the testbench establishment of Smart Card IC, which shows that this method effiectively improves the efficiency of verification. Besides, the scripts develop in this project can be reused by other projects which can save plenty of time.