Design Of USB3.1 System-Level Verification Platform Based On UVM

As the design of the chip becomes more and more complex,the pre-RTL level functional verification becomes more and more important in the chip development process.USB-based electronic products are commonly used in daily life.In order to meet the rapid development of large-scale storage,USB organizations continue to upgrade technology,USB standard specification has been developed from 1.0,2.0,3.0 to 3.1,whose data transfer speed has been increased to lOGbps.With the improvement of performance,in order to ensure the correct function of the SoC chip,complete functional verification of the USB 3.1 IP is necessary.In view of the above situation,the subject has analyzed the verification methodology widely used at present.The UVM verification architecture developed from SystemVerilog has been adopted by many IC design companies for its scalability and reusability,and is currently the most advanced verification method.According to the characteristics of the project and verification requirements,this paper selected the UVM methodology to implement the USB 3.1 functional verification.In the process of implementation of the verifying environment,need to study USB 3.1 specification at first,including the contents of the USB 3.1 system architecture and the contents of the physical layer,link layer,and protocol layer,which is defined in the specification,and then functional test points are proposed according to this.Then planning the environment according to the test points,use the UVM-based verification component to build the verification platform,and use the TLM method provided by UVM to complete the connection between the verification components so that a complete data path can be formed in the environment.Later,according to the proposed functional test points to write test sequences,and use the random function of System Verilog to create random test cases,and finally to achieve a reusable,parameterized random verification environment based on UVM verification methodology,And use this verification environment to carry out a reliable and complete verification of USB 3.1 system-level functions.Finally,analyze the coverage rate according to the simulation results.Adding uncovered functional verification points by modifying or adding directional sequences ensures product quality.In general,the verification environment judges whether the DUT function is correct by driving an sequence to the input of the DUT and then observing the state of the DUT internal signals and responding to the output signal of the stimulus.But even for a large number of random tests for complex IP verification.Still can't monitor the state of all key signals in DUT well.In this regard,this paper proposes a SVA module design method based on UVM verification component.Adding an assertion module in the UVM verification component not only solves the limitations caused by traditional verification,but also makes the assertion module reusable.