RapidIO Links Design And Analysis On ATCA Platform

In recent years, with the development of the embedded system, an advanced requirement of data transmission is raised for the system designers, which result in the appearances of a variety of new types of serial bus technologies. Among these technologies, serial RapidIO becomes more and more popular in the embedded system for its high performance, high reliability, and flexible structure, RapidIO has thus become the only international standard for embedded system interconnects. This topic is based on the design of 60 GHz high-speed wireless transmission baseband platform, the platform uses ATCA architecture and there are two pieces of FPGA on a single board, we use serial RapidIO protocol for high speed data transfer between the two FPGAs. We also add a RapidIO Switch to the board for future expansion and upgrades, this thesis is about the RapidIO links design and test of the entire system platform.At first, this thesis deeply studied the RapidIO interconnect architecture and the ATCA platform, analyzed the the logical layer, the transport layer and the physical layer of the RapidIO protocol respectively. The thesis also analyzed the structure and key technologies of each layer and focused on RapidIO packet format and transaction operation process. The study of ATCA platform mainly cared for serial RapidIO backplane which is used for high-speed signal transmission between the daughter boards.Then according to the study of RapidIO protocol, the thesis designed the point-to-point Rapid IO links based on Xilinx’s SRIO endpoint IP core and Virtex 7 series FPGA for 60 GHz wireless transmission high-speed baseband platform. The thesis also designed the user interface based on asynchronous FIFO for data transmission with different clock domains and different reading and writing width. After completion of the design, the thesis verified the link both in simulation environment and the Printed Circuit Board, including testing the connectivity, the time delay and the bandwidth of the RapidIO links.At last, considering the demand to extend and upgrade the system in the future, as well as to achieve flexibility of the RapidIO networking, on the basis of the point-to-point direct RapidIO links between two FPGAs, the thesis designed switching RapidIO links based on the second generation of IDT’s serial RapidIO switch CPS-1848. The links were divided into two parts, the first part were single-board RapidIO switch links, the second part were RapidIO links that transmitted across the ATCA backplane. The main content include the design of the connections between the CPS-1848 and the backplane, the configuration of the CPS-1848, the connectivity test of the RapidIO links and the performance tests of the entire RapidIO system, etc.