A Novel All Digital Phase-locked Loop Design And Implementation Based On FPGA

Phase-locked loop(PLL) is a closed-loop feedback control system, which can effectively track the phase and frequency of the input signal. Phase-locked loop has been widely applied in areas such as communications, automation and power system, due to its excellent performance, it has become the important and indispensable basic components of all kinds of electronic systems. Compared with analog phase-locked loop, all digital phase-locked loop(ADPLL) has many advantages, such as stable parameters, strong anti-interference ability and easy integration and so on. In addition, ADPLL solves the problems that existing in analog phase-locked loop that nonlinear of voltage-controlled oscillator, low phase detecting precision of phase discriminator, components easy to saturation, and instability of the high order system. Therefore, ADPLL is applied more and more.So far, the structure and control methods of ADPLL are varied, and short lock time, small synchronous error, large range of frequency tracking and strong anti-interference ability is a standard which can judge stand or fall of the PLL system. The fixed control parameter in the design of traditional ADPLL will lead to the problem that frequency tracking range is relatively narrow, and so, this paper designed a kind of enhanced PLL which was adopted by a method of adaptive control and PI control to realize, and it can solve the problem very well. This PLL can make the loop bandwidth changes automatically along with the change of the input signal frequency. Moreover, the traditional ADPLL have a problem that the locking speed and anti-interference ability cannot be coordinated each other, so the adaptive controller is designed according to the size of the phase error in this paper and it make the capture process divide into three process: the fast acquisition area, transition area and slow catching area, and it make the control parameters of the ADPLL adjust with these three process automatically. So the adaptive controller can solve the contradiction between the loop locking time and noise resistance effectively. Furthermore, when the input signal frequency suddenly change, the traditional ADPLL will start the long locking process again. To address this problem, this paper designed a frequency control word preset circuit which can make the loop lock the input signal in one cycle, so this circuits reduce the locking time greatly.On the basis of the study about the loop module and analysis the whole mathematical model of the ADPLL, the whole system circuit was finally designed which was adopted by the top-down idea of modular design, and then the circuit was compiled, synthesized and simulated in the Quartus II software environment, finally, the design result was tested on the FPGA. The function simulation in the software and the actual test results show that:the loop bandwidth of the designed ADPLL change with the frequency of the input signal, and the locking time is shorter and the synchronization error is smaller than the traditional ADPLL of PI control, and can be applied to the system with fast synchronization requirements. When the system clock is 50 MHz and the loop frequency coefficient is N = 64, the loop slowest locking time is 8 cycles of the input signal, when the loop is stable, the fastest can be completed in one cycle, the synchronous error is ? 160 ns, the frequency tracking range is 40 Hz ~ 390 KHz. In addition, this ADPLL has characteristics of its simple structure and easy integration.