Research On The Verification Of Network Packet Parser Based On UVM Methlodogy

The rapid development of VLSI increases the integration of chip and the complexity of chip design which has made a great challenge for functional verification work. The traditional functional verification method has many defects in reusability, verification efficiency, the function coverage and so on. So it has become a bottleneck in the development of IC design. Looking for a new verification method is imminent. The UVM(Universal Verification Methodology) launched by Accellera organization has solved the defect of traditional verification platform and leads the development of IC verification. This thesis researches and implements a UVM verification platform with a SystemVerilog verification language which is based on a network packet parser prototype. At the same time, it’s required that the code coverage must achieve more than 95% and the function coverage must achieve 100%.First, three main technologies for functional verification are analyzed in the thesis: transaction-based verification, coverage-driven verification and assertion-based verification, which has obvious advantages compared to traditional functional verification. Then, some advantages of SystemVerilog compared with Verilog and SystemC are also analyzed in the thesis, such as support coverage, assertions, random validation, error injection, excellent memory management and so on. UVM combines the benefits of three verification technology with the advantages of SystemVerilog language together, and forms a hierarchical UVM tree structure and a sound work mechanism. According to these features of UVM, a system verification scheme is proposed in the thesis after an analysis about the functional requirements of network packet parser, finally an overall UVM verification platform architecture is designed.Second, according to the platform architecture, all components of the UVM verification platform will be implemented in this thesis. The implementation of two core components are mainly analyzed: Frame_generator and Parser_rm. For different test case scenarios(random and directed verification), Sequence generates four types of frames: short frame, long frame, mixed frame and error frame. At the same time Parser_rm implements a reference parser as a standard comparison model which has the same functional characteristics of DUT. In addition, to make sure the verification is complete, all coverage points which are designed in coverage group in Monitor component are required to achieve the covering convergence.At the last, the function simulation of DUT has been completed in this thesis and the performance of the UVM verification platform has also been analyzed. The result of the parser’s functional verification which has combined the advantage of random testcase and directed testcase is that the code coverage has achieved 98.96% and the function coverage has achieved 100%. This indicates that the functional verification to the parser is fully complete and the parser is always working well.