The Comparison Strategies And Reconfiguration Of Ring Oscillator Physicalunclonable Functions

With the development of information technology, security and private issues are becoming more and more important. Physical Unclonable Function(PUF) is a new kind of hardware-based security primitives, which attracts lots of research interests for more than one decade. PUFs have the ability to extract the fabrication variations of integrated circuits(IC) and use them to generate unique responses. Due to the characteristics of unclonability, uniqueness, unpredictability of PUFs, they are suitable for device authentication, IP protection, key generation and so on.Firstly, the PUF principle, classifications, characteristics, structures are introduced and overviewed in Chapter 1. In Chapter 2, one of the classical PUF structure, Ring Oscillator(RO) PUF, is reviewed. The design of both the Challenge/Response Pairs(CRPs) support and CRPs non-support RO PUFs are discussed. In addition, RO array is introduced in details as it is the core part of a RO PUF and it is directly related to the quality of RO PUF. In order to implement a high quality RO PUF in FPGA, the techniques including Xilinx Hard Macro creation, ROs placement are used in the implementation of RO array.Secondly, RO PUF response extraction strategies i.e. RO comparison strategies are studied, which is closely related to the security of RO PUF. By statistically analyzing ROs’ oscillation frequencies in 193 FPGAs, three RO frequency distribution characteristics are summarized. According to the discovered characteristics, three new RO comparison strategies are proposed. Five different comparison strategies are evaluated, and the results show that the proposed symmetric comparison strategy has the best responses in terms of entropy density. Furthermore, the evaluation results illustrate that these distribution characteristics are very important to improve RO PUF design.Thirdly, a novel PUF structure, Reconfigurable RO(RRO) PUF, is proposed in this thesis. RRO PUF is designed to reduce the hardware consumption and improve response uniqueness of RO PUF. The structure, work principle and hardware cost of RRO PUF are analyzed, and a RRO comparison strategy for RRO PUF is proposed in this thesis. In addition, the RRO circuit characteristics in Xilinx Spartan-6 FPGA and the adjustments that are applied to design RRO PUF in FPGA are also presented. Based on the experiment results, it is clear that RRO PUFs have higher hardware efficiency and better response uniqueness compared with that of conventional RO PUFs.